As the degree of integration in semiconductor devices increases, dimensions and wire widths in the integrated circuits continue to shrink. Accordingly, fabrication of semiconductor devices is becoming more complex and demanding. For instance, when a photolithography process is performed to pattern circuitry on a wafer, the possibility of misalignment increases due to down-scaling, and thus unwanted patterns may be formed.
FIG. 1 is a view of a semiconductor device 100. The semiconductor device 100 includes a substrate 110, a poly-silicon gate 120, a spacer 125, a silicide layer 121, and a dielectric layer 150. When the height of the spacer 125 is equal to or lower than that of the gate 120, the silicide layer 121 often has a mushroom shape and may extrude beyond the boundary of the gate 120, as depicted in FIG. 1. Therefore, a contact metal 160 (e.g., tungsten or copper) on a source/drain region 115 might form a short circuit at 129 with the gate 120 via silicide layer 121, as a result of misalignment during the photolithography process for forming the contact opening on the source/drain region 115. Such short-circuiting between the gate 120 and the source/drain contact, i.e., contact metal 160, increases the population of defective cells. Further, such short-circuits increase the overall manufacturing cost because of rework processes to fix such defective cells, and consumption of additional materials such as photoresist and chemical solvents. The short-circuiting problems are further worsened as the silicide layer 121, which is provided to increase the conductivity of the gate 120, tends to extrude outwardly to the top of the spacer 125 and form an undesirable short-circuit with contact metal 160 when photolithographic misalignment occurs. The gate 120 can also be a metal gate in which case no silicide formation is formed on the metal gate 120. However, if photolithographic misalignment occurs, short circuits are also likely to occur.